tc74vhc373f/ft/fk 2010-08-18 1 toshiba cmos digital integrat ed ci rcuit silicon monolithic tc74vhc373f,tc74vhc373ft,tc74vhc373fk octal d-type latch with 3-state output the tc74vhc373 is an advanced high speed cmos octal latch with 3-state output fabr icated with silicon gate c 2 mos technology. it achieves the high speed op eration similar to equivalent bipolar schottky ttl while ma intaining the cmos low power dissipation. this 8-bit d-type latch is co ntrolled by a latch enable input (le) and an output enable input ( oe ). when the oe input is high, the eight outputs are in a high impedance state. an input protection circuit en sures that 0 to 5.5 v can be applied to the input pins withou t regard to the supply voltage. this device can be used to interface 5 v to 3 v systems and two supply systems such as battery back up. this circuit prevents device destruction due to mismat ched supply and input voltages. features ? high speed: t pd = 5.0 ns (typ.) at v cc = 5 v ? low power dissipation: i cc = 4 a (max) at ta = 25c ? high noise immunity: v nih = v nil = 28% v cc (min) ? power down protection is provided on all inputs. ? balanced propagation delays: t plh ? t phl ? wide operating voltage range: v cc (opr) = 2 to 5.5 v ? low noise: v olp = 0.9 v (max) ? pin and function compatible with 74als373 weight sop20-p-300-1.27a : 0.22 g (typ.) tssop20-p-0044-0.65a : 0.08 g (typ.) vssop20-p-0030-0.50 : 0.03 g (typ.) tc74vhc373f tc74vhc373ft tc74vhc373fk
tc74vhc373f/ft/fk 2010-08-18 2 pin assignment iec logic symbol truth table inputs oe le d output h x x z l l x q n l h l l l h h h x: don?t care z: high impedance q n : q outputs are latched at the time when the le input is taken to a low logic level. system diagram v cc 16 d6 q6 q5 15 14 13 12 11 20 oe 1 2 3 4 5 6 7 q2 d2 d3 q3 q0 d5 8 d7 19 d4 q7 d1 q1 18 9 d0 gnd 10 le 17 q4 (top view) (17) (13) (14) (11) (1) (3) (7) (4) d1 1d d3 d2 (8) d5 d4 (2) (6) (12) q1 q3 q5 (5) (9) (15) q2 q4 q6 en c1 le oe d6 (18) d7 (16) q7 (19) q0 d0 oe le 11 3 2 l q d q1 d1 5 l q d q2 d2 6 l q d q3 d3 9 l q d q4 d4 12 l q d q5 d5 15 l q d q6 d6 16 l q d q7 d7 19 l q d q0 d0 4 7 8 13 14 17 18 1 d
tc74vhc373f/ft/fk 2010-08-18 3 absolute maximum ratings (note) characteristics symbol rating unit supply voltage range v cc ?0.5 to 7.0 v dc input voltage v in ?0.5 to 7.0 v dc output voltage v out ?0.5 to v cc + 0.5 v input diode current i ik ?20 ma output diode current i ok 20 ma dc output current i out 25 ma dc v cc /ground current i cc 75 ma power dissipation p d 180 mw storage temperature t stg ?65 to 150 c note: exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in ic performance or even destruction. using continuously under heavy loads (e.g. the app lication of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temper ature/current/voltage, etc. ) are within the absolute maximum ratings and the operating ranges. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook (?handling precautions?/?derating concept and methods?) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). operating ranges (note ) characteristics symbol rating unit supply voltage v cc 2.0 to 5.5 v input voltage v in 0 to 5.5 v output voltage v out 0 to v cc v operating temperature t opr ?40 to 85 c input rise and fall time dt/dv 0 to 100 (v cc = 3.3 0.3 v) 0 to 20 (v cc = 5 0.5 v) ns/v note: the operating ranges must be maintained to ensure the normal oper ation of the device. unused inputs must be tied to either v cc or gnd.
tc74vhc373f/ft/fk 2010-08-18 4 electrical characteristics dc characteristics test condition ta = 25c ta = 40 to 85c characteristics symbol v cc (v) min typ. max min max unit high-level input voltage v ih ? 2.0 3.0 to 5.5 1.50 v cc 0.7 ? ? ? ? 1.50 v cc 0.7 ? ? v low-level input voltage v il ? 2.0 3.0 to 5.5 ? ? ? ? 0.50 v cc 0.3 ? ? 0.50 v cc 0.3 v i oh = 50 a 2.0 3.0 4.5 1.9 2.9 4.4 2.0 3.0 4.5 ? ? ? 1.9 2.9 4.4 ? ? ? high-level output voltage v oh v in = v ih or v il i oh = 4 ma i oh = 8 ma 3.0 4.5 2.58 3.94 ? ? ? ? 2.48 3.80 ? ? v i ol = 50 a 2.0 3.0 4.5 ? ? ? 0.0 0.0 0.0 0.1 0.1 0.1 ? ? ? 0.1 0.1 0.1 low-level output voltage v ol v in = v ih or v il i ol = 4 ma i ol = 8 ma 3.0 4.5 ? ? ? ? 0.36 0.36 ? ? 0.44 0.44 v 3-state output off-state current i oz v in = v ih or v il v out = v cc or gnd 5.5 ? ? 0.25 ? 2.50 a input leakage current i in v in = 5.5 v or gnd 0 to 5.5 ? ? 0.1 ? 1.0 a quiescent supply current i cc v in = v cc or gnd 5.5 ? ? 4.0 ? 40.0 a timing requirements (input: t r = t f = 3 ns) test condition ta = 25c ta = 40 to 85c characteristics symbol v cc (v) typ. limit limit unit minimum pulse width (le) t w (h) ? 3.3 0.3 5.0 0.5 ? ? 5.0 5.0 5.0 5.0 ns minimum set-up time t s ? 3.3 0.3 5.0 0.5 ? ? 4.0 4.0 4.0 4.0 ns minimum hold time t h ? 3.3 0.3 5.0 0.5 ? ? 1.0 1.0 1.0 1.0 ns
tc74vhc373f/ft/fk 2010-08-18 5 ac electrical characteristics (input: t r = t f = 3 ns) test condition ta = 25c ta = 40 to 85c characteristics symbol v cc (v) c l (pf) min typ. max min max unit 15 ? 7.0 11.0 1.0 13.0 3.3 0.3 50 ? 9.5 14.5 1.0 16.5 15 ? 4.9 7.2 1.0 8.5 propagation delay time (le-q) t plh t phl ? 5.0 0.5 50 ? 6.4 9.2 1.0 10.5 ns 15 ? 7.3 11.4 1.0 13.5 3.3 0.3 50 ? 9.8 14.9 1.0 17.0 15 ? 5.0 7.2 1.0 8.5 propagation delay time (d-q) t plh t phl ? 5.0 0.5 50 ? 6.5 9.2 1.0 10.5 ns 15 ? 7.3 11.4 1.0 13.5 3.3 0.3 50 ? 9.8 14.9 1.0 17.0 15 ? 5.5 8.1 1.0 9.5 3-state output enable time t pzl t pzh r l = 1 k
5.0 0.5 50 ? 7.0 10.1 1.0 11.5 ns 3.3 0.3 50 ? 9.5 13.2 1.0 15.0 3-state output disable time t plz t phz r l = 1 k
5.0 0.5 50 ? 6.5 9.2 1.0 10.5 ns 3.3 0.3 50 ? ? 1.5 ? 1.5 output to output skew t oslh t oshl (note 1) 5.0 0.5 50 ? ? 1.0 ? 1.0 ns input capacitance c in ? ? 4 10 ? 10 pf output capacitance c out ? ? 6 ? ? ? pf power dissipation capacitance c pd (note 2) ? 27 ? ? ? pf note 1: parameter guaranteed by design. t oslh = |t plhm t plhn |, t oshl = |t phlm t phln | note 2: c pd is defined as the value of the internal equivalent capacitance which is ca lculated from the operating current consumption without load. average operating current can be obtained by the equation: i cc (opr) = c pd v cc f in + i cc /8 (per latch) and the total c pd when n pcs. of latch operate can be gained by the following equation: c pd (total) = 14 + 13n
tc74vhc373f/ft/fk 2010-08-18 6 noise characteristics (input: t r = t f = 3 ns) test condition ta = 25c characteristics symbol v cc (v) typ. max unit quiet output maximum dynamic v ol v olp c l = 50 pf 5.0 0.5 0.8 v quiet output minimum dynamic v ol v olv c l = 50 pf 5.0 0.5 0.8 v minimum high level dynamic input voltage v ihd c l = 50 pf 5.0 ? 3.5 v maximum low level dynamic input voltage v ild c l = 50 pf 5.0 ? 1.5 v input equivalent circuit input
tc74vhc373f/ft/fk 2010-08-18 7 package dimensions weight: 0.22 g (typ.)
tc74vhc373f/ft/fk 2010-08-18 8 package dimensions weight: 0.08 g (typ.)
tc74vhc373f/ft/fk 2010-08-18 9 package dimensions weight: 0.03 g (typ.)
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